\doxysubsubsubsection{MDMA interrupt enable definitions }
\hypertarget{group___m_d_m_a__interrupt__enable__definitions}{}\label{group___m_d_m_a__interrupt__enable__definitions}\index{MDMA interrupt enable definitions@{MDMA interrupt enable definitions}}


MDMA interrupt enable definitions.  


\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___m_d_m_a__interrupt__enable__definitions_ga9cc92aced4ae74acc42b4201dfcba4ec}{MDMA\+\_\+\+IT\+\_\+\+TE}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafdddcb23d16c5fbb6a163556116fbd4c}{MDMA\+\_\+\+CCR\+\_\+\+TEIE}})
\item 
\#define \mbox{\hyperlink{group___m_d_m_a__interrupt__enable__definitions_gad9bdf660da9ac5d3ff87f402d81ef15b}{MDMA\+\_\+\+IT\+\_\+\+CTC}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadefa541e6bb5062f0ecae2c7f95c5082}{MDMA\+\_\+\+CCR\+\_\+\+CTCIE}})
\item 
\#define \mbox{\hyperlink{group___m_d_m_a__interrupt__enable__definitions_ga8087099dd207338786417b28ff6da606}{MDMA\+\_\+\+IT\+\_\+\+BRT}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5e458b1dc9663cb5bce66d8bbbccd8c6}{MDMA\+\_\+\+CCR\+\_\+\+BRTIE}})
\item 
\#define \mbox{\hyperlink{group___m_d_m_a__interrupt__enable__definitions_gac8b95cb719cca95fb4ab91951a19c7ef}{MDMA\+\_\+\+IT\+\_\+\+BT}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac46954a8902b70f858d54d921e3a81d2}{MDMA\+\_\+\+CCR\+\_\+\+BTIE}})
\item 
\#define \mbox{\hyperlink{group___m_d_m_a__interrupt__enable__definitions_gaa1bd825795cff50c3c2ba5b3d5f90ddb}{MDMA\+\_\+\+IT\+\_\+\+BFTC}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga68296065030eebca929a4006c2974f03}{MDMA\+\_\+\+CCR\+\_\+\+TCIE}})
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
MDMA interrupt enable definitions. 



\label{doc-define-members}
\Hypertarget{group___m_d_m_a__interrupt__enable__definitions_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___m_d_m_a__interrupt__enable__definitions_gaa1bd825795cff50c3c2ba5b3d5f90ddb}\index{MDMA interrupt enable definitions@{MDMA interrupt enable definitions}!MDMA\_IT\_BFTC@{MDMA\_IT\_BFTC}}
\index{MDMA\_IT\_BFTC@{MDMA\_IT\_BFTC}!MDMA interrupt enable definitions@{MDMA interrupt enable definitions}}
\doxysubsubsubsubsubsection{\texorpdfstring{MDMA\_IT\_BFTC}{MDMA\_IT\_BFTC}}
{\footnotesize\ttfamily \label{group___m_d_m_a__interrupt__enable__definitions_gaa1bd825795cff50c3c2ba5b3d5f90ddb} 
\#define MDMA\+\_\+\+IT\+\_\+\+BFTC~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga68296065030eebca929a4006c2974f03}{MDMA\+\_\+\+CCR\+\_\+\+TCIE}})}

Buffer Transfer Complete interrupt \Hypertarget{group___m_d_m_a__interrupt__enable__definitions_ga8087099dd207338786417b28ff6da606}\index{MDMA interrupt enable definitions@{MDMA interrupt enable definitions}!MDMA\_IT\_BRT@{MDMA\_IT\_BRT}}
\index{MDMA\_IT\_BRT@{MDMA\_IT\_BRT}!MDMA interrupt enable definitions@{MDMA interrupt enable definitions}}
\doxysubsubsubsubsubsection{\texorpdfstring{MDMA\_IT\_BRT}{MDMA\_IT\_BRT}}
{\footnotesize\ttfamily \label{group___m_d_m_a__interrupt__enable__definitions_ga8087099dd207338786417b28ff6da606} 
\#define MDMA\+\_\+\+IT\+\_\+\+BRT~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5e458b1dc9663cb5bce66d8bbbccd8c6}{MDMA\+\_\+\+CCR\+\_\+\+BRTIE}})}

Block Repeat Transfer interrupt \Hypertarget{group___m_d_m_a__interrupt__enable__definitions_gac8b95cb719cca95fb4ab91951a19c7ef}\index{MDMA interrupt enable definitions@{MDMA interrupt enable definitions}!MDMA\_IT\_BT@{MDMA\_IT\_BT}}
\index{MDMA\_IT\_BT@{MDMA\_IT\_BT}!MDMA interrupt enable definitions@{MDMA interrupt enable definitions}}
\doxysubsubsubsubsubsection{\texorpdfstring{MDMA\_IT\_BT}{MDMA\_IT\_BT}}
{\footnotesize\ttfamily \label{group___m_d_m_a__interrupt__enable__definitions_gac8b95cb719cca95fb4ab91951a19c7ef} 
\#define MDMA\+\_\+\+IT\+\_\+\+BT~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac46954a8902b70f858d54d921e3a81d2}{MDMA\+\_\+\+CCR\+\_\+\+BTIE}})}

Block Transfer interrupt \Hypertarget{group___m_d_m_a__interrupt__enable__definitions_gad9bdf660da9ac5d3ff87f402d81ef15b}\index{MDMA interrupt enable definitions@{MDMA interrupt enable definitions}!MDMA\_IT\_CTC@{MDMA\_IT\_CTC}}
\index{MDMA\_IT\_CTC@{MDMA\_IT\_CTC}!MDMA interrupt enable definitions@{MDMA interrupt enable definitions}}
\doxysubsubsubsubsubsection{\texorpdfstring{MDMA\_IT\_CTC}{MDMA\_IT\_CTC}}
{\footnotesize\ttfamily \label{group___m_d_m_a__interrupt__enable__definitions_gad9bdf660da9ac5d3ff87f402d81ef15b} 
\#define MDMA\+\_\+\+IT\+\_\+\+CTC~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadefa541e6bb5062f0ecae2c7f95c5082}{MDMA\+\_\+\+CCR\+\_\+\+CTCIE}})}

Channel Transfer Complete interrupt \Hypertarget{group___m_d_m_a__interrupt__enable__definitions_ga9cc92aced4ae74acc42b4201dfcba4ec}\index{MDMA interrupt enable definitions@{MDMA interrupt enable definitions}!MDMA\_IT\_TE@{MDMA\_IT\_TE}}
\index{MDMA\_IT\_TE@{MDMA\_IT\_TE}!MDMA interrupt enable definitions@{MDMA interrupt enable definitions}}
\doxysubsubsubsubsubsection{\texorpdfstring{MDMA\_IT\_TE}{MDMA\_IT\_TE}}
{\footnotesize\ttfamily \label{group___m_d_m_a__interrupt__enable__definitions_ga9cc92aced4ae74acc42b4201dfcba4ec} 
\#define MDMA\+\_\+\+IT\+\_\+\+TE~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafdddcb23d16c5fbb6a163556116fbd4c}{MDMA\+\_\+\+CCR\+\_\+\+TEIE}})}

Transfer Error interrupt 